1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to the method for manufacturing stacked CMOS semiconductor devices.
2. Description of the Prior Art
Since this invention produces most desirable results when applied to a fabrication process of a CMOS (Complementary Metal Oxide Semiconductor) static RAM (Random Access Memory), it should be noted that the present invention will be described hereinafter in connection with the CMOS static RAM without necessarilly intending to limit the invention thereto.
A CMOS static RAM or CMOS is conventionally known and the typical structure of such prior art CMOS SRAM is shown in FIG. 1. Referring now to FIG. 1, the SRAM includes a memory cell array 41 in which a plurality of word lines and a plurality of the lines are arranged to intersect with each other. A memory cell 40 is provided at each of the intersections or junctions of the word lines and bit lines. The SRAM also includes an X decoder 42 and a Y decoder 43 which operate to select one of the word lines and one of the bit lines, respectively, at a time whereby selecting a particular memory cell at a junction of the selected word line and the selected bit line. In a data writing operation, input data or Din is fed to the selected memory cell, while in a data read-out operation, the data stored in the selected memory cell is read out and then amplified by a sense amplifier 44 before it is fed out as output data or Dout.
FIG. 2 illustrates schematically an equivalent circuit of any one 40 of the memory cells in the memory cell array 41 of the CMOS shown in FIG. 1. The memory cell 40 includes n-channel MOS transistors T5, T6 which form a gate circuit, and a pair of CMOS inverters, one being comprised of p-channel MOS transistors T1, T3 and the other being comprised of n-channel MOS transistors T2, T4. The gates of MOS transistors T5, T6 are both connected to the word line 35, while each one of the remaining two electrodes in transistors T5, T6 is connected to the bit line 33, 34, respectively.
With this general construction, when it is intended to read out the data stored in a memory cell, a predetermined voltage is applied on the word line 35, and then voltages appears on the bit line 33, 34, the levels of which corresponds to the state of the respective inverters T1-T2, T3-T4. On the other hand, when it is desired to write data into the memory cell, a predetermined voltage is first applied on the word line 35, and then write-in voltage is impressed on the bit lines 33, 34.
FIGS. 3A to 3C illustrate, step by step, the prior art process of manufacturing a pattern layout for the memory cell. As shown in FIG. 3A, there is formed on the surface of the p-channel semiconductor substrate 1, N type well 51 and N type diffusion regions 27. P type diffusion region 26 is then formed on the N type well 51. Also formed on the preselected area of the substrate surface are a word line 35a and gate layers 35 (FIG. 3B). Thereafter as shown in FIG. 3C, ground conductors 31, 32 and bit lines 33, 34 are formed of aluminum. Aluminum conductors 61, 62 are provided. The aluminum conductor 61 is provided for supplying source voltage Vcc to the N type well 51 through p-type diffusion layer 26, and the aluminum conductor 62 for connecting the gate layer 35 with the diffusion regions 26 and 27. More specifically, the aluminum conductor 61 connects N type well region 51 and the p-type diffusion layer 26 via a contact 6a, while the aluminum conductor 62 connects the diffusion layers 26 and 27 through contacts 6b and 7a, respectively. The aluminum conductor 62 is also communicated to the gate layers 35 via a contact 6c. The ground conductors 31, 32 are coupled with the N type diffusion layer 27 via a contact 7c, and the bit lines 33, 34 are also coupled with the N type diffusion region 27 via still another contact 7b.
FIGS. 4A to 4G illustrate schematically the steps of fabricating a CMOS inverter incorporated in the memory cell of the prior art SRAM. It should be pointed out that these figures show a portion of the memory cell in cross section as taken along lines IV--IV.
According to the conventional process, there is formed on a p-channel silicon substrate 1 a silicon oxide layer 101 using, for example, a thermal oxidation technique. The silicon nitride layer 102 is provided over the silicon oxide layer 101 (FIG. 4A). Using this silicon nitride layer 102 as a mask, a selective oxidation is carried out to obtain a thick silicon oxide layer 103, and the remaining silicon nitride layer 102 is removed. Next, using the thick silicon oxide layer 103 as a mask, phosphorus ions are implanted into the p-type silicon substrate 1 by means of an ion injection technique (FIG. 4B).
Now the substrate is subject to a heat treatment in order to diffuse the phosphorus ions into the substrate, resulting in the formation of a N type well 51. Then another silicon oxide layer 104 and silicon nitride layer 105 are provided over the silicon substrate 1 in a similar manner previously described. Utilizing photoresist 106 formed on the prescribed region of the two layers 104, 105 as a mask, portions of the silicon nitride layer 105 are etched away FIG. 4C). Using the silicon nitride again as a mask, another selective oxidation is preformed to obtain a thick field oxide layer 107. When the desired field oxide layer 107 is formed, the silicon nitride layer 105 and the silicon oxide layer 14 are both removed. As shown in FIG. 4D, after depositing a gate oxide layer 110, a plurality of polysilicon layers 109a-109d are formed. In the step illustrated in FIG. 4E, boron ions are injected or implanted into the substrate 1 in order to selectively form p-type diffusion layer 26. Arsenic ions are similarly injected to selectively obtain n-type diffusion layer 27. The formation of p-type diffusion layer 26 results in the formation of a p-type field effect transistor T3, while the formation of the n-type diffusion layer brings about the formation of n-type field effect transistor T4 (FIG. 4E).
In the next step shown in FIG. 4F, a silicon oxide layer 111 is again deposited over the substrate to cover its upper surface as by CVD Chemical Vapor Deposition). A plurality of contact holes 6b, 6c and 7a are made in the silicon oxide layer 111 by using photolithography and etching operations. An aluminum conductor 62 is formed and the resulting device is covered by a passivation layer 112 (FIG. 4G).
In the past, the CMOS inverter which is included in a memory cell in the prior art SRAM was fabricated according to the process described above. And in the prior art process, the CMOS inverter was made in the form of a single planar layer, thus making it difficult to integrate component elements. For the purpose of improving the integration of the device, a stacked CMOS structure or arrangement has recently being proposed and adopted by the design engineers.
FIG. 5A to 5F are partial cross sections of a typical stacked CMOS structure showing various steps of manufacturing the same. Referring first to FIG. 5A, there is formed on a p-type silicon substrate 1 a silicon oxide layer 2 as by using the thermal oxidation operation. On this silicon oxide layer 2, phosphorous doped polysilicon layer is deposited using, for example, a CVD process under low pressure conditions. Then a gate electrode 3 is formed on the silicon oxide layer 2 by the standard photolithography and etching techniques. Arsenic ions are implanted in a self-alignment manner with the gate electrode acting as a mask and, as a result, a n-type MOS transistor comprising source 4, drain 5 and channel region 6 is obtained (FIG. 5B).
A silicon oxide layer 7 is provided as by the thermal oxidation so that the layer covers the gate electrode 3. By means of the known photolithography or etching technique, an aperture or opening 8 is made in the silicon oxide layer 2 at a position above the drain region 5 of the n-channel MOS transistor (FIG. 5C). Subsequent to this step, a polysilicon layer 16 is disposed as by CVD under low pressure conditions (FIG. 5D). Then, a photoresist 17 is patterned on the prescribed region of the polysilicon layer 16 by the photolithographic process, after which boron ions are implanted using the resist 17 as a mask (FIG. 5E). Upon removing the resist 17, the entire substrate 1 is then subject to a heat treatment, resulting in the formation of p-channel MOS transistor comprising source 12, drain 13 and channel region 14 (FIG. 5F). It should be noted here that drain 5 of the n-channel MOS transistor mentioned above and source 12 of this p-channel MOS transistor are connected each other via the opening 8, thus establishing a p-n junction of the CMOS structure.
The operation of the stacked CMOS is now explained. Here we define that the threshold voltage for the p-channel MOS transistor at V.sub.TP and threshold voltage for the n-channel MOS transistor at V.sub.TN (where V.sub.TN &gt; V.sub.TP). The drain of the p-channel MOS transistor is connected to a positive potential V.sub.DD, while the source of the n-channel MOS transistor is connected to ground with a voltage V.sub.CC being applied to the common gate electrode 3. If the gate potential V.sub.CC is higher than the threshold voltage V.sub.TN of the n-channel MOS transistor, that is V.sub.CC &gt; V.sub.TN, then the n-channel MOS transistor is kept ON, while the p-channel MOS. transistor is kept OFF. On the other hand, if the threshold voltage V.sub.TP of the p-channel MOS transistor is higher than the gate potential V.sub.CC or V.sub.TP &gt; V.sub.CC, then p-channel MOS transistor is ON, while the n-channel MOS transistor is OFF.
In this manner with the stacked CMOS, ON an OFF states of the two different transistors, that is the n-and p-channel MOS transistors can be controlled by one and the same gate electrode 3 which is common to the both MOS transistors.
In the prior art method of manufacturing stacked semiconductor devices, source 12 and drain 13 of the p-channel MOS transistor are formed by the implant of boron ions. However, this boron implantation involves the use of the resist 17 as a mask, which causes a serious problem because, when the resist is disposed by the photolithographic process, it is absolutely necessary for the resist 17 to precisely overlap over or align with the gate electrode 3. It is no easy task to control the relative position of the resist to the gate electrode so that the former accurately overlaps with the latter. Another problem inherent in the prior art method resides in the fact that the distance between the source 12 and the drain 13 of the p-channel MOS transistor, that is the geometrical length L of the channel 14 as shown in FIG. 5F is dependent on the size R of the resist 17 as indicated in FIG. 5E. Stated differently, the length L of channel 14 is depending on the size R of the resist 17. Under the circumstances, it has been found that when stacked type semiconductor devices are manufactured on the mass production basis, it is extremely difficult to obtain the semiconductor devices having uniform performance characteristics because the characteristics of the p-channel MOS transistor, for example, its threshold voltage V.sub.TP changes according to the difference in the size R of the resist.
Another problem has also been pointed out. In the prior art process, the source 12, drain 13 and channel region 14 of the p-channel MOS transistor are all made of polysilicon layer. As can be readily understood by one skilled in the art, the polysilicon layer includes a countless number of grains and grain-boundaries, and therefore the layer does not have a complete crystalline structure. Due to this grain structure of the polysilicon layer, if there is potential difference between the source 12 and drain 13 of the p-channel MOS transistor while it is in OFF state, a leakage current flows between the source and the drain. This is undesirable because it contributes to an increased power consumption by the stacked semiconductor devices.
In order to avoid and overcome the above mentioned problems associated with the prior art manufacturing process, it has been proposed to build the p-channel MOS transistor using a self-aligned process as described in the article "A fully self-aligned stacked CMOS 64K SRAM" (R.Sundaresam et. al., IDEM 84, pp. 871-873).
FIG. 6A to 6C schematically illustrate some important steps in the fully self-aligned process disclosed in the article. According to this improved process, a stacked CMOS is manufactured as follows. On a semiconductor substrate 1, there are formed gate electrode 3, source region 4 and drain region 5 by using the steps previously discussed in connection with FIGS. 5A to 5C. A second polysilicon layer 16 is deposited on the gate electrode 3 with an insulating layer being interposed therebetween. A boron doped oxide layer 18 is then spun on top of the second polysilicon layer 16 (FIG. 6A). A plasma etch is used to remove the oxide from directly above the channel region leaving a sidewall structure (FIG. 6B). After deposition of cap oxide layer 19, a thermal anneal in an inner ambient drives in the boron from oxide into the polysilicon layer 16 to form the source and drain regions. The cap oxide layer 19 and the spin-on oxide layer 18 are then removed using a wet etchant (FIG. 6C).
With the improved process for the manufacture of stacked CMOS device having these steps, the source and drain of the p-channel MOS transistor are formed in a fully self-aligned manner, thus eliminating the complicated mask overlapping or alignment step.
However, the proposed fully self-aligned process still possesses some shortcomings. One shortcoming is that the sidewall structure of the boron doped oxide layer 18 which has grown on the polysilicon layer 16 is to be removed after the source and drain regions 4, 5 have been formed. Thus the polysilicon layer 16 comprising the source and drain regions is the same in thickness as it has been initially formed. In other words, the thickness of the polysilicon layer does not increase and, as a result, the electrical resistance of the polysilicon layer remains relatively large, which gives rise to the possibility that the read out operation in the transistor device is rather slow. Another possible shortcoming stems also from the same fact as pointed above. That is, the sidewall structure of the boron ion doped oxide layer 18 is to be removed after the formation of the source and drain regions as illustrated in FIG. 6C, thus the p-channel MOS transistor tends to have a sharp corners in its source and drain regions 4, 5, which renders the upper surface of the MOS transistor device uneven or irregular. This irregular surface, in turn, makes it difficult to patternize aluminum conductor layers on the surface of the resulted transistor.